1. Field of the Invention
The present invention relates to a communication controller for multiplex communication based on SDLC and HDLC protocols.
2. Description of the Prior Art
Referring to FIG. 7, there is shown a prior art serial communication controller in which data lines (TXD, RXD) are not multiplexed. Referring to FIG. 8, there is also shown a prior art serial communication controller which has two channels, but the data lines of channels A and B are separated from each other.
A description is subsequently given of the operation of these controllers. The communication controller shown in FIG. 7 outputs transmission data (TXD) and receives reception data (RXD) in synchronism with a clock (CLK). Moreover, data are written and read by a CPU.
The communication controller shown in FIG. 8 has two data lines for each of transmission data and reception data but the operation is the same as above.
Since the prior art communication controllers are structured as described above, it is necessary to increase the number of circuits having the same configuration as the number of channels grows in order to handle a large number of channels. Since the number of LSIs must be increased, these communication controllers have such problems as an increase in the amount of hardwares and a rise in costs. They also have the problem that the CPU bus is used exclusively for DMA (Direct Memory Access) in order to transfer data from an external memory with the result of lowered performance of the device.